Settings for registers of 3D Hall 15 I2C Click driver. More...

Macros
#define	C3DHALL15I2C_CTRL1_START_SAMPLE_CLEAR 0x0000
	3D Hall 15 I2C CTRL1 register setting.
#define	C3DHALL15I2C_CTRL1_START_SAMPLE_SET 0x1000
#define	C3DHALL15I2C_CTRL1_START_SAMPLE_MASK 0x1000
#define	C3DHALL15I2C_CTRL1_INTERRUPT_FLAG_CLEAR 0x0000
#define	C3DHALL15I2C_CTRL1_INTERRUPT_FLAG_SET 0x0800
#define	C3DHALL15I2C_CTRL1_INTERRUPT_FLAG_MASK 0x0800
#define	C3DHALL15I2C_CTRL1_STATUS_READY_CLEAR 0x0000
#define	C3DHALL15I2C_CTRL1_STATUS_READY_SET 0x0400
#define	C3DHALL15I2C_CTRL1_STATUS_READY_MASK 0x0400
#define	C3DHALL15I2C_CTRL1_SLEEP_CNT_0_68_MS 0x0000
#define	C3DHALL15I2C_CTRL1_SLEEP_CNT_1_36_MS 0x0010
#define	C3DHALL15I2C_CTRL1_SLEEP_CNT_6_82_MS 0x0020
#define	C3DHALL15I2C_CTRL1_SLEEP_CNT_13_64_MS 0x0030
#define	C3DHALL15I2C_CTRL1_SLEEP_CNT_68_18_MS 0x0040
#define	C3DHALL15I2C_CTRL1_SLEEP_CNT_136_36_MS 0x0050
#define	C3DHALL15I2C_CTRL1_SLEEP_CNT_681_82_MS 0x0060
#define	C3DHALL15I2C_CTRL1_SLEEP_CNT_1363_64_MS 0x0070
#define	C3DHALL15I2C_CTRL1_SLEEP_CNT_MASK 0x0070
#define	C3DHALL15I2C_CTRL1_OP_MODE_ACTIVE 0x0000
#define	C3DHALL15I2C_CTRL1_OP_MODE_ACTIVE_INT 0x0002
#define	C3DHALL15I2C_CTRL1_OP_MODE_ACTIVE_SAM 0x0004
#define	C3DHALL15I2C_CTRL1_OP_MODE_SLEEP 0x0006
#define	C3DHALL15I2C_CTRL1_OP_MODE_SLEEP_SAM 0x0008
#define	C3DHALL15I2C_CTRL1_OP_MODE_LPDCM_INT 0x000A
#define	C3DHALL15I2C_CTRL1_OP_MODE_LPDCM 0x000C
#define	C3DHALL15I2C_CTRL1_OP_MODE_MASK 0x000E
#define	C3DHALL15I2C_CTRL2_INT_THR_MSB_DIR_MASK 0x0F00
	3D Hall 15 I2C CTRL2 register setting.
#define	C3DHALL15I2C_CTRL2_INT_THR_LSB_DIR_MASK 0x00FF
#define	C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Z_DIR_EN 0x0000
	3D Hall 15 I2C CTRL3 register setting.
#define	C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Z_DIR_DIS 0x2000
#define	C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Z_DIR_MASK 0x2000
#define	C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Y_DIR_EN 0x0000
#define	C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Y_DIR_DIS 0x1000
#define	C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Y_DIR_MASK 0x1000
#define	C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_X_DIR_EN 0x0000
#define	C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_X_DIR_DIS 0x0800
#define	C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_X_DIR_MASK 0x0800
#define	C3DHALL15I2C_CTRL3_POL_F_Z_DIR_NORMAL 0x0000
#define	C3DHALL15I2C_CTRL3_POL_F_Z_DIR_INVERTED 0x0400
#define	C3DHALL15I2C_CTRL3_POL_F_Z_DIR_MASK 0x0400
#define	C3DHALL15I2C_CTRL3_POL_F_Y_DIR_NORMAL 0x0000
#define	C3DHALL15I2C_CTRL3_POL_F_Y_DIR_INVERTED 0x0200
#define	C3DHALL15I2C_CTRL3_POL_F_Y_DIR_MASK 0x0200
#define	C3DHALL15I2C_CTRL3_POL_F_X_DIR_NORMAL 0x0000
#define	C3DHALL15I2C_CTRL3_POL_F_X_DIR_INVERTED 0x0100
#define	C3DHALL15I2C_CTRL3_POL_F_X_DIR_MASK 0x0100
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_X 0x0000
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_Y 0x0008
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_Z 0x0010
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_ABS_X 0x0018
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_ABS_Y 0x0020
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_ABS_Z 0x0028
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_TEMP 0x0030
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_ANGLE 0x0038
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_RADIUS 0x0040
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_NEW_SAMPLE 0x0048
#define	C3DHALL15I2C_CTRL3_INT_SEL_DIR_MASK 0x0078
#define	C3DHALL15I2C_CTRL3_INT_SIGN_DIR_LESS 0x0000
#define	C3DHALL15I2C_CTRL3_INT_SIGN_DIR_GREATER 0x0004
#define	C3DHALL15I2C_CTRL3_INT_SIGN_DIR_MASK 0x0004
#define	C3DHALL15I2C_CTRL3_INT_FLAG_LATCH_DIR_DIS 0x0000
#define	C3DHALL15I2C_CTRL3_INT_FLAG_LATCH_DIR_EN 0x0002
#define	C3DHALL15I2C_CTRL3_INT_FLAG_LATCH_DIR_MASK 0x0002
#define	C3DHALL15I2C_CTRL3_SAMPLE_INT_POL_DIR_LOW 0x0001
#define	C3DHALL15I2C_CTRL3_SAMPLE_INT_POL_DIR_HIGH 0x0001
#define	C3DHALL15I2C_CTRL3_SAMPLE_INT_POL_DIR_MASK 0x0001
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_195_5_HZ 0x0000
	3D Hall 15 I2C CTRL4 register setting.
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_391_HZ 0x0100
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_782_HZ 0x0200
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_1564_HZ 0x0300
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_3128_HZ 0x0400
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_6256_HZ 0x0500
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_12512_HZ 0x0600
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_MASK 0x0700
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_195_5_HZ 0x0000
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_391_HZ 0x0010
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_782_HZ 0x0020
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_1564_HZ 0x0030
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_3128_HZ 0x0040
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_6256_HZ 0x0050
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_12512_HZ 0x0060
#define	C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_MASK 0x0070
#define	C3DHALL15I2C_CTRL4_CORDIC_POL_DIR_NORMAL 0x0000
#define	C3DHALL15I2C_CTRL4_CORDIC_POL_DIR_INVERTED 0x0008
#define	C3DHALL15I2C_CTRL4_CORDIC_POL_DIR_MASK 0x0008
#define	C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_X_SINE_Y 0x0000
#define	C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_X_SINE_Z 0x0001
#define	C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Y_SINE_Z 0x0002
#define	C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Y_SINE_X 0x0003
#define	C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Z_SINE_X 0x0004
#define	C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Z_SINE_Y 0x0005
#define	C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_MASK 0x0007
#define	C3DHALL15I2C_TEMP_SIGN_BIT 0x0800
	3D Hall 15 I2C data calculation setting.
#define	C3DHALL15I2C_TEMP_SIGN_MASK 0xF000
#define	C3DHALL15I2C_TEMP_RES 8.052
#define	C3DHALL15I2C_TEMP_OFFSET 25.0
#define	C3DHALL15I2C_XYZ_SIGN_BIT 0x4000
#define	C3DHALL15I2C_XYZ_SIGN_MASK 0x8000
#define	C3DHALL15I2C_XYZ_RES_MT 268.0
#define	C3DHALL15I2C_ANGLE_RES_DEG 0.0109863
#define	C3DHALL15I2C_DEVICE_ADDRESS 0x65
	3D Hall 15 I2C device address setting.

Detailed Description

Settings for registers of 3D Hall 15 I2C Click driver.

Macro Definition Documentation

◆ C3DHALL15I2C_ANGLE_RES_DEG

#define C3DHALL15I2C_ANGLE_RES_DEG 0.0109863

◆ C3DHALL15I2C_CTRL1_INTERRUPT_FLAG_CLEAR

#define C3DHALL15I2C_CTRL1_INTERRUPT_FLAG_CLEAR 0x0000

◆ C3DHALL15I2C_CTRL1_INTERRUPT_FLAG_MASK

#define C3DHALL15I2C_CTRL1_INTERRUPT_FLAG_MASK 0x0800

◆ C3DHALL15I2C_CTRL1_INTERRUPT_FLAG_SET

#define C3DHALL15I2C_CTRL1_INTERRUPT_FLAG_SET 0x0800

◆ C3DHALL15I2C_CTRL1_OP_MODE_ACTIVE

#define C3DHALL15I2C_CTRL1_OP_MODE_ACTIVE 0x0000

◆ C3DHALL15I2C_CTRL1_OP_MODE_ACTIVE_INT

#define C3DHALL15I2C_CTRL1_OP_MODE_ACTIVE_INT 0x0002

◆ C3DHALL15I2C_CTRL1_OP_MODE_ACTIVE_SAM

#define C3DHALL15I2C_CTRL1_OP_MODE_ACTIVE_SAM 0x0004

◆ C3DHALL15I2C_CTRL1_OP_MODE_LPDCM

#define C3DHALL15I2C_CTRL1_OP_MODE_LPDCM 0x000C

◆ C3DHALL15I2C_CTRL1_OP_MODE_LPDCM_INT

#define C3DHALL15I2C_CTRL1_OP_MODE_LPDCM_INT 0x000A

◆ C3DHALL15I2C_CTRL1_OP_MODE_MASK

#define C3DHALL15I2C_CTRL1_OP_MODE_MASK 0x000E

◆ C3DHALL15I2C_CTRL1_OP_MODE_SLEEP

#define C3DHALL15I2C_CTRL1_OP_MODE_SLEEP 0x0006

◆ C3DHALL15I2C_CTRL1_OP_MODE_SLEEP_SAM

#define C3DHALL15I2C_CTRL1_OP_MODE_SLEEP_SAM 0x0008

◆ C3DHALL15I2C_CTRL1_SLEEP_CNT_0_68_MS

#define C3DHALL15I2C_CTRL1_SLEEP_CNT_0_68_MS 0x0000

◆ C3DHALL15I2C_CTRL1_SLEEP_CNT_1363_64_MS

#define C3DHALL15I2C_CTRL1_SLEEP_CNT_1363_64_MS 0x0070

◆ C3DHALL15I2C_CTRL1_SLEEP_CNT_136_36_MS

#define C3DHALL15I2C_CTRL1_SLEEP_CNT_136_36_MS 0x0050

◆ C3DHALL15I2C_CTRL1_SLEEP_CNT_13_64_MS

#define C3DHALL15I2C_CTRL1_SLEEP_CNT_13_64_MS 0x0030

◆ C3DHALL15I2C_CTRL1_SLEEP_CNT_1_36_MS

#define C3DHALL15I2C_CTRL1_SLEEP_CNT_1_36_MS 0x0010

◆ C3DHALL15I2C_CTRL1_SLEEP_CNT_681_82_MS

#define C3DHALL15I2C_CTRL1_SLEEP_CNT_681_82_MS 0x0060

◆ C3DHALL15I2C_CTRL1_SLEEP_CNT_68_18_MS

#define C3DHALL15I2C_CTRL1_SLEEP_CNT_68_18_MS 0x0040

◆ C3DHALL15I2C_CTRL1_SLEEP_CNT_6_82_MS

#define C3DHALL15I2C_CTRL1_SLEEP_CNT_6_82_MS 0x0020

◆ C3DHALL15I2C_CTRL1_SLEEP_CNT_MASK

#define C3DHALL15I2C_CTRL1_SLEEP_CNT_MASK 0x0070

◆ C3DHALL15I2C_CTRL1_START_SAMPLE_CLEAR

#define C3DHALL15I2C_CTRL1_START_SAMPLE_CLEAR 0x0000

3D Hall 15 I2C CTRL1 register setting.

Specified setting for CTRL1 register of 3D Hall 15 I2C Click driver.

◆ C3DHALL15I2C_CTRL1_START_SAMPLE_MASK

#define C3DHALL15I2C_CTRL1_START_SAMPLE_MASK 0x1000

◆ C3DHALL15I2C_CTRL1_START_SAMPLE_SET

#define C3DHALL15I2C_CTRL1_START_SAMPLE_SET 0x1000

◆ C3DHALL15I2C_CTRL1_STATUS_READY_CLEAR

#define C3DHALL15I2C_CTRL1_STATUS_READY_CLEAR 0x0000

◆ C3DHALL15I2C_CTRL1_STATUS_READY_MASK

#define C3DHALL15I2C_CTRL1_STATUS_READY_MASK 0x0400

◆ C3DHALL15I2C_CTRL1_STATUS_READY_SET

#define C3DHALL15I2C_CTRL1_STATUS_READY_SET 0x0400

◆ C3DHALL15I2C_CTRL2_INT_THR_LSB_DIR_MASK

#define C3DHALL15I2C_CTRL2_INT_THR_LSB_DIR_MASK 0x00FF

◆ C3DHALL15I2C_CTRL2_INT_THR_MSB_DIR_MASK

#define C3DHALL15I2C_CTRL2_INT_THR_MSB_DIR_MASK 0x0F00

3D Hall 15 I2C CTRL2 register setting.

Specified setting for CTRL2 register of 3D Hall 15 I2C Click driver.

◆ C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_X_DIR_DIS

#define C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_X_DIR_DIS 0x0800

◆ C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_X_DIR_EN

#define C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_X_DIR_EN 0x0000

◆ C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_X_DIR_MASK

#define C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_X_DIR_MASK 0x0800

◆ C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Y_DIR_DIS

#define C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Y_DIR_DIS 0x1000

◆ C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Y_DIR_EN

#define C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Y_DIR_EN 0x0000

◆ C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Y_DIR_MASK

#define C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Y_DIR_MASK 0x1000

◆ C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Z_DIR_DIS

#define C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Z_DIR_DIS 0x2000

◆ C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Z_DIR_EN

#define C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Z_DIR_EN 0x0000

3D Hall 15 I2C CTRL3 register setting.

Specified setting for CTRL3 register of 3D Hall 15 I2C Click driver.

◆ C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Z_DIR_MASK

#define C3DHALL15I2C_CTRL3_AFE_CHAN_DIS_Z_DIR_MASK 0x2000

◆ C3DHALL15I2C_CTRL3_INT_FLAG_LATCH_DIR_DIS

#define C3DHALL15I2C_CTRL3_INT_FLAG_LATCH_DIR_DIS 0x0000

◆ C3DHALL15I2C_CTRL3_INT_FLAG_LATCH_DIR_EN

#define C3DHALL15I2C_CTRL3_INT_FLAG_LATCH_DIR_EN 0x0002

◆ C3DHALL15I2C_CTRL3_INT_FLAG_LATCH_DIR_MASK

#define C3DHALL15I2C_CTRL3_INT_FLAG_LATCH_DIR_MASK 0x0002

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_ABS_X

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_ABS_X 0x0018

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_ABS_Y

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_ABS_Y 0x0020

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_ABS_Z

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_ABS_Z 0x0028

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_ANGLE

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_ANGLE 0x0038

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_MASK

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_MASK 0x0078

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_NEW_SAMPLE

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_NEW_SAMPLE 0x0048

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_RADIUS

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_RADIUS 0x0040

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_TEMP

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_TEMP 0x0030

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_X

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_X 0x0000

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_Y

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_Y 0x0008

◆ C3DHALL15I2C_CTRL3_INT_SEL_DIR_Z

#define C3DHALL15I2C_CTRL3_INT_SEL_DIR_Z 0x0010

◆ C3DHALL15I2C_CTRL3_INT_SIGN_DIR_GREATER

#define C3DHALL15I2C_CTRL3_INT_SIGN_DIR_GREATER 0x0004

◆ C3DHALL15I2C_CTRL3_INT_SIGN_DIR_LESS

#define C3DHALL15I2C_CTRL3_INT_SIGN_DIR_LESS 0x0000

◆ C3DHALL15I2C_CTRL3_INT_SIGN_DIR_MASK

#define C3DHALL15I2C_CTRL3_INT_SIGN_DIR_MASK 0x0004

◆ C3DHALL15I2C_CTRL3_POL_F_X_DIR_INVERTED

#define C3DHALL15I2C_CTRL3_POL_F_X_DIR_INVERTED 0x0100

◆ C3DHALL15I2C_CTRL3_POL_F_X_DIR_MASK

#define C3DHALL15I2C_CTRL3_POL_F_X_DIR_MASK 0x0100

◆ C3DHALL15I2C_CTRL3_POL_F_X_DIR_NORMAL

#define C3DHALL15I2C_CTRL3_POL_F_X_DIR_NORMAL 0x0000

◆ C3DHALL15I2C_CTRL3_POL_F_Y_DIR_INVERTED

#define C3DHALL15I2C_CTRL3_POL_F_Y_DIR_INVERTED 0x0200

◆ C3DHALL15I2C_CTRL3_POL_F_Y_DIR_MASK

#define C3DHALL15I2C_CTRL3_POL_F_Y_DIR_MASK 0x0200

◆ C3DHALL15I2C_CTRL3_POL_F_Y_DIR_NORMAL

#define C3DHALL15I2C_CTRL3_POL_F_Y_DIR_NORMAL 0x0000

◆ C3DHALL15I2C_CTRL3_POL_F_Z_DIR_INVERTED

#define C3DHALL15I2C_CTRL3_POL_F_Z_DIR_INVERTED 0x0400

◆ C3DHALL15I2C_CTRL3_POL_F_Z_DIR_MASK

#define C3DHALL15I2C_CTRL3_POL_F_Z_DIR_MASK 0x0400

◆ C3DHALL15I2C_CTRL3_POL_F_Z_DIR_NORMAL

#define C3DHALL15I2C_CTRL3_POL_F_Z_DIR_NORMAL 0x0000

◆ C3DHALL15I2C_CTRL3_SAMPLE_INT_POL_DIR_HIGH

#define C3DHALL15I2C_CTRL3_SAMPLE_INT_POL_DIR_HIGH 0x0001

◆ C3DHALL15I2C_CTRL3_SAMPLE_INT_POL_DIR_LOW

#define C3DHALL15I2C_CTRL3_SAMPLE_INT_POL_DIR_LOW 0x0001

◆ C3DHALL15I2C_CTRL3_SAMPLE_INT_POL_DIR_MASK

#define C3DHALL15I2C_CTRL3_SAMPLE_INT_POL_DIR_MASK 0x0001

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_12512_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_12512_HZ 0x0060

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_1564_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_1564_HZ 0x0030

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_195_5_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_195_5_HZ 0x0000

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_3128_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_3128_HZ 0x0040

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_391_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_391_HZ 0x0010

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_6256_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_6256_HZ 0x0050

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_782_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_782_HZ 0x0020

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_MASK

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_DIR_MASK 0x0070

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_12512_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_12512_HZ 0x0600

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_1564_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_1564_HZ 0x0300

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_195_5_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_195_5_HZ 0x0000

3D Hall 15 I2C CTRL4 register setting.

Specified setting for CTRL4 register of 3D Hall 15 I2C Click driver.

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_3128_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_3128_HZ 0x0400

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_391_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_391_HZ 0x0100

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_6256_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_6256_HZ 0x0500

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_782_HZ

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_782_HZ 0x0200

◆ C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_MASK

#define C3DHALL15I2C_CTRL4_CIC_BW_SEL_LPM_DIR_MASK 0x0700

◆ C3DHALL15I2C_CTRL4_CORDIC_POL_DIR_INVERTED

#define C3DHALL15I2C_CTRL4_CORDIC_POL_DIR_INVERTED 0x0008

◆ C3DHALL15I2C_CTRL4_CORDIC_POL_DIR_MASK

#define C3DHALL15I2C_CTRL4_CORDIC_POL_DIR_MASK 0x0008

◆ C3DHALL15I2C_CTRL4_CORDIC_POL_DIR_NORMAL

#define C3DHALL15I2C_CTRL4_CORDIC_POL_DIR_NORMAL 0x0000

◆ C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_X_SINE_Y

#define C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_X_SINE_Y 0x0000

◆ C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_X_SINE_Z

#define C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_X_SINE_Z 0x0001

◆ C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Y_SINE_X

#define C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Y_SINE_X 0x0003

◆ C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Y_SINE_Z

#define C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Y_SINE_Z 0x0002

◆ C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Z_SINE_X

#define C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Z_SINE_X 0x0004

◆ C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Z_SINE_Y

#define C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_COS_Z_SINE_Y 0x0005

◆ C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_MASK

#define C3DHALL15I2C_CTRL4_CORDIC_SEL_DIR_MASK 0x0007

◆ C3DHALL15I2C_DEVICE_ADDRESS

#define C3DHALL15I2C_DEVICE_ADDRESS 0x65

3D Hall 15 I2C device address setting.

Specified setting for device slave address selection of 3D Hall 15 I2C Click driver.

◆ C3DHALL15I2C_TEMP_OFFSET

#define C3DHALL15I2C_TEMP_OFFSET 25.0

◆ C3DHALL15I2C_TEMP_RES

#define C3DHALL15I2C_TEMP_RES 8.052

◆ C3DHALL15I2C_TEMP_SIGN_BIT

#define C3DHALL15I2C_TEMP_SIGN_BIT 0x0800

3D Hall 15 I2C data calculation setting.

Specified setting for data calculation of 3D Hall 15 I2C Click driver.

◆ C3DHALL15I2C_TEMP_SIGN_MASK

#define C3DHALL15I2C_TEMP_SIGN_MASK 0xF000

◆ C3DHALL15I2C_XYZ_RES_MT

#define C3DHALL15I2C_XYZ_RES_MT 268.0

◆ C3DHALL15I2C_XYZ_SIGN_BIT

#define C3DHALL15I2C_XYZ_SIGN_BIT 0x4000

◆ C3DHALL15I2C_XYZ_SIGN_MASK

#define C3DHALL15I2C_XYZ_SIGN_MASK 0x8000

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